1. Field of the Invention
The present invention relates to a circuit arrangement for driving a gate of a transistor, in particular a MOSFET. The invention also relates to a method for driving a gate of such a transistor.
2. Description of the Related Art
Prior Art
Circuit arrangements for driving gates of transistors are known. Such a known circuit arrangement is illustrated in FIG. 1. The circuit arrangement 1 comprises a MOS transistor 11, which is electrically connected with its gate 111 to a gate series resistor 12. The gate series resistor 12 is electrically connected to a pulsed DC voltage source 13. As can further be seen in FIG. 1, the drain terminal 112 of the MOS transistor 11 is connected to a load resistor 14, this load resistor 14 being electrically connected to a voltage source 15. Furthermore, the source terminal 113 of the MOS transistor 11 is connected to ground potential. The circuit arrangement 1 illustrated in FIG. 1 is arranged in an electronic ballast, which is used for operating and adjusting fluorescent lamps.
FIG. 2 shows three different signal profiles V1, V2 and I, which are tapped off at points V1, V2 and I in FIG. 1. As can be seen in this case in FIG. 2, the signal profile V1 characterizes a digital voltage profile. The signal profile V2 characterizes the voltage profile at the gate 111 of the MOS transistor 11. Furthermore, the illustration in FIG. 2 represents the signal profile I, which characterizes the current profile 114 through the load resistor 14.
As can be seen from the illustration in FIG. 2, the gate series resistor 12 is switched over from 100 ohms to 400 ohms at time t=55 μs. As can be seen in this case, the signal profile V2 at the gate 111 of the transistor 11 is thus altered and, as a result, the edge steepness of the load current through the load resistor 14 is altered directly, in accordance with the signal profile I. Owing to the change in the switching speed, two opposing properties can be seen. On the one hand, when the resistance value of the gate series resistor 12 is reduced, the switching losses in the circuit arrangement 1 are likewise reduced. However, when there is such a reduction in the resistance value of the gate series resistor 12, the electromagnetic interference (EMI) is increased. When the resistance value of the gate series resistor 12 is increased, the switching losses of the circuit arrangement 1 are increased, in which case the electromagnetic interference is reduced. In practice, it was now possible also to observe the fact that the permissible EMI limit values of an electronic operating device, which is represented, for example, by the HTi DALI 150/220-240 DIM, are not exceeded at dimming settings of the electronic ballast which are substantially greater than 1% of a maximum dimming setting. However, if dimming settings are set which are approximately in the range between 0.1% and 1%, it was possible to establish that the permissible limit values for the electronic converter are being exceeded.
In order to counteract such a case of the permissible limit values being exceeded, in particular at the abovementioned dimming settings, an increase in the gate series resistance was set, as a result of which the EMI response can be improved at all dimming settings. One significant disadvantage with such a procedure, however, is the fact that the power loss is increased at all dimming settings. This in turn leads to relatively high losses in the overall embodiment of an electronic device, in which such a MOS transistor having such a drive circuit is arranged. For example, it is thus necessary for the housing in which the circuit arrangement, in particular the transistor, is arranged to be designed to be larger or for the permissible ambient temperature to be reduced.